Welcome to IEEE TCCA Email-Monthly, Jan. 2005. 1. New papers published online by Computer Architecture Letters *Website: *Submitted by: Kevin Skadron 2. HPCA-11: 11th INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE *February 12-16, 2005, Palace Hotel, San Francisco, CA *Deadline for early registration: Jan. 16th, 2005 *Submitted by: Christoforos Kozyrakis * http://www.hpcaconf.org/hpca11 3. MoBS: Workshop on Modeling, Benchmarking, and Simulation *Madison, Wisconsin, June 4-5, 2005 *SUBMISSION DEADLINE: 9 PM (CST) March 7, 2005 *Submitted by: Joshua J. Yi jjyi@ece.umn.edu *CALL FOR PAPERS http://www.arctic.umn.edu/MoBS 4. ANCHOR 2005: Advanced Networking and Communications Hardware Workshop *Madison, Wisconsin, June 4-8 2005 *SUBMISSION DEADLINE: April 1st, 2005 *Submitted by: Taskin Kocak *CALL FOR PAPERS http://www.ece.northwestern.edu/anchor 5. ICS05: The 19th ACM International Conference on Supercomputing *Cambridge, Massachusetts,June 20 - 22, 2005 *SUBMISSION DEADLINE: February 8, 2005 *Submitted by: Sally Lee *CALL FOR PAPERS http://ics05.csail.mit.edu/ ------- * Archive: http://www.ele.uri.edu/tcca * To submit an email message to be distributed among TCCA members, send an email to qyang@ele.uri.edu * To subscribe to this mailing list, please sign up at * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe ----------------------------------------------------------------------- Qing (Ken) Yang, Professor Distinguished Engineering Professor e-mail: qyang@ele.uri.edu Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 University of Rhode Island Fax (401) 782-6422 Kingston RI. 02881 http://www.ele.uri.edu/~qyang ------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ New papers published online by Computer Architecture Letters Computer Architecture Letters announces our three most recent papers, which are publicly available at . We continue to seek new submissions and remain committed to fast and accurate review. Our mean time to decision remains one month, with an acceptance rate of approximately 21%. For more information on submission, please see our website. - L. Ceze, K. Strauss, J. Tuck, J. Renau, J. Torrellas. "CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction." Volume 3, Dec. 2004. - A. Singh, W. J. Dally. "Buffer and Delay Bounds in High Radix Interconnection Networks." Volume 3, Dec. 2004. - A. L. Holloway, G. S. Sohi. "Characterization of Problem Stores." Volume 3, Dec. 2004. Abstracts --------- - L. Ceze, K. Strauss, J. Tuck, J. Renau, J. Torrellas. "CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction." Volume 3, Dec. 2004. Abstract: Load misses in on-chip L2 caches often end up stalling modern superscalars. To address this problem, we propose hiding L2 misses with Checkpoint-Assisted VAlue prediction (CAVA). When a load misses in L2, a predicted value is returned to the processor. If the missing load reaches the head of the reorder buffer before the requested data is received from memory, the processor checkpoints, consumes the predicted value, and speculatively continues execution. When the requested data finally arrives, it is compared to the predicted value. If the prediction was correct, execution continues normally; otherwise, execution rolls back to the checkpoint. Compared to a baseline aggressive superscalar, CAVA speeds up execution by a geometric mean of 1.14 for SPECint and 1.34 for SPECfp applications. Additionally, CAVA is faster than an implementation of Runahead execution, and Runahead with value prediction. - A. Singh, W. J. Dally. "Buffer and Delay Bounds in High Radix Interconnection Networks." Volume 3, Dec. 2004. Abstract: We apply recent results in queueing theory to propose a methodology for bounding the buffer depth and packet delay in high radix interconnection networks. While most work in interconnection networks has been focused on the throughput and average latency in such systems, few studies have been done providing statistical guarantees for buffer depth and packet delays. These parameters are key in the design and performance of a network. We present a methodology for calculating such bounds for a practical high radix network and through extensive simulations show its effectiveness for both bursty and non-bursty injection traffic. Our results suggest that modest speedups and buffer depths enable reliable networks without flow control to be constructed. - A. L. Holloway, G. S. Sohi. "Characterization of Problem Stores." Volume 3, Dec. 2004. Abstract: This paper introduces the concept of problem stores: static stores whose dependent loads often miss in the cache. Accurately identifying problem stores allows the early determination of addresses likely to cause later misses, potentially allowing for the development of novel, proactive prefetching and memory hierarchy management schemes. We present a detailed empirical characterization of problem stores using the SPEC2000 CPU benchmarks. The data suggests several key observations about problem stores. First, we find that the number of important problem stores is typically quite small; the worst 100 problem stores write the values that will lead to about 90\% of non-cold misses for a variety of cache configurations. We also find that problem stores only account for 1 in 8 dynamic stores, though they result in 9 of 10 misses. Additionally, the problem stores' dependent loads miss in the L2 cache a larger fraction of the time than loads not dependent on problem stores. We also observe the set of problem stores is stable across a variety of cache configurations. Finally, we found that the instruction distance from problem store to miss and problem store to evict is often greater than one million instructions, but the value is often needed within 100,000 instructions of the eviction. ****************************************************** 11th INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE (HPCA-11) February 12-16, 2005 Palace Hotel, San Francisco, CA http://www.hpcaconf.org/hpca11 ****************************************************** Important Reminders - Deadline for conference hotel discount: Jan. 11th, 2005 - Deadline for early registration: Jan. 16th, 2005 (note the hotel discount deadline is earlier) 2005 Conference Higlights - 3 tutorials and 6 workshops - 28 regular papers - Industrial perspectives session with 6 foward looking papers from IBM, Intel, Sun, and HP, including a paper on the cell processor - Keynote speech by Fred Weber, CTO, AMD on "Trends in High Performance Processors" ============================ DETAILED CONFERENCE PROGRAM ============================ Saturday February 12, 2005 ============================ 8:30-5:00 All Day Events Tutorial T2: All You Want To Know About Circuits As An Architect But Were Afraid To Ask Shih-Lien Lu, MRL/MTL Intel Steven Hsu, CRL/MTL Intel Workshop W1: CAECW-8: Computer Architecture Evaluation using Commercial Workloads Kimberly Keeton, HP Labs Lieven Eeckhout, Ghent University Pankaj Mehra, HP Ravi Iyer, Intel Labs Russell Clapp, Fabric7 Systems, Inc. Workshop W2: HPCRI: High Performance Computing Reliability Issues Padma Apparao, Intel LabsINDUSTRIAL PERSPECTIVES Greg Averill, Intel Labs 1:00-5:00 Afternoon Events Tutorial T1: A Practical Approach To Performance Analysis And Modeling Of Large-Scale Systems Adolfy Hoisie, Los Alamos National Laboratory Darren Kerbyson, Los Alamos National Laboratory Sunday February 13, 2005 ============================ 8:30-12:00 Morning Events Tutorial T3: Volatile Memory Performance Comparison J. Thomas Pawlowski, Micron Technology, Inc. 8:30-5:00 All Day Events Workshop W4: INTERACT-9: Interaction between Compilers and Computer Architectures Gyungho Lee, University of Illinois at Chicago Wei-Chung Hsu, University of Minnesota Workshop W5: PPHEC-2: Productivity and Performance in High-End Computing Ram Rajamony, IBM Workshop W6: Hardware Performance Monitor Design and Functionality Olaf Lubeck, Los Alamos National Laboratory Phil Mucci, University of Tennessee Mike Lang, Los Alamos National Laboratory Rob Fowler, Rice University 1:00-5:00 Afternoon Events Workshop W3: Architecture Research using FPGA Platforms Arvind, MIT Krste Asanovic, MIT Derek Chiou, UT Austin James Hoe, CMU Christoforos Kozyrakis, Stanford Shih-Lien Lu, Intel 6:30-8:00 Reception at the hotel Monday February 14, 2005 ============================== 8:15-8:30 Welcome 8:30-9:30 Keynote Speech: "Trends in High-Performance Processors" Fred Weber, Chief Technology Officer, AMD Chair: Josep Torrellas 9:30-10:00 Break 10:00-12:00 SESSION 1: PROCESSOR ARCHITECTURE Chair: Antonio Gonzalez, Universitat Politecnica de Catalunya and Intel Labs Multithreaded Value Prediction Nathan Tuck, University of California, San Diego Dean M. Tullsen, University of California, San Diego Checkpointed Early Load Retirement Nevin Kirman, Cornell University Meyrem Kirman, Cornell University Mainak Chaudhuri, Cornell University Jose F. Martinez, Cornell University Microarchitectural Wire Management for Performance and Power in Partitioned Architectures Rajeev Balasubramonian, University of Utah Naveen Muralimanohar, University of Utah Karthik Ramani, University of Utah Venkatanand Venkatachalapathy, University of Utah A Small, Fast and Low-Power Register File by Bit-Partitioning Masaaki Kondo, University of Tokyo Hiroshi Nakamura, University of Tokyo 12:00-1:30 Intel-sponsored lunch 1:30-3:30 SESSION 2: TEMPERATURE, ENERGY, AND POWER Chair: Krste Asanovic, MIT Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses Krishnan Sundaresan, Michigan State University Nihar R. Mahapatra, Michigan State University Distributing the Frontend for Temperature Reduction Pedro Chaparro Monferrer, Universitat Politecnica de Catalunya and Intel Labs Grigorios Magklis, Universitat Politecnica de Catalunya and Intel Labs Jose Gonzalez, Universitat Politecnica de Catalunya and Intel Labs Antonio Gonzalez, Universitat Politecnica de Catalunya and Intel Labs Performance, Energy, and Thermal Considerations for SMT and CMP Architectures Yingmin Li University of Virginia David Brooks Harvard University Zhigang Hu IBM T.J.Watson Research Center Kevin Skadron University of Virginia Tapping ZettaRAM for Low-Power Memory Systems Ravi K. Venkatesan, North Carolina State University Ahmed S. AL-Zawawi, North Carolina State University Eric Rotenberg, North Carolina State University 3:30-4:00 Break 4:00-6:00 SESSION 3: COMMUNICATION ARCHITECTURES Chair: Timothy Pinkston, University of Southern California An Efficient Programmable 10 Gigabit Ethernet Network Interface Card Paul Willmann, Rice University Hyong-youb Kim, Rice University Scott Rixner, Rice University Vijay S. Pai, Purdue University A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks J. Duato, Universitat Politecnica de Valencia, Spain I. Johnson, Xyratex, United Kingdom J. Flich, Universitat Politecnica de Valencia, Spain F. Naven, Xyratex, United Kingdom P. Garc???a, Universidad de Castilla-La Mancha, Spain T. Nachiondo, Universitat Politecnica de Valencia, Spain Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems Xuning Chen, Princeton University Yue-kai Huang, Princeton University Li-Shiuan Peh, Princeton University Paul Prucnal, Princeton University Gu-Yeon Wei, Harvard University Scatter-Add in Data Parallel Architectures Jung Ho Ahn, Stanford University Mattan Erez, Stanford University Bill Dally, Stanford University 6:30-8:00 TCCA Business Meeting Tuesday February 15, 2004 ============================== 8:00-10:00 SESSION 4: ENERGY AND POWER Chair: Yuanyuan Zhou, University of Illinois Software Assisted Issue Queue Power Reduction Timothy M. Jones, University of Edinburgh Michael F. P. O'Boyle, University of Edinburgh Jaume Abella, Universitat Politecnica de Catalunya Antonio Gonzalez, Universitat Politecnica Catalunya and Intel Labs On the Limits of Leakage Power Reduction in Caches Yan Meng, University of California, Santa Barbara Timothy Sherwood, University of California, Santa Barbara Ryan Kastner, University of California, Santa Barbara Heat Stroke: Power-Density-Based Denial of Service in SMT Jahangir Hasan, Purdue University Ankit Jalote, Purdue University T. N. Vijaykumar, Purdue University Carla Brodley, Tufts University Voltage and Frequency Control with Adaptive Reaction Time in Multiple-Clock-Domain Processors Qiang Wu, Princeton University Philo Juang, Princeton University Margaret Martonosi, Princeton University Douglas W. Clark, Princeton University 10:00-10:30 Break 10:30-12:30 SESSION 5: MEMORY SYSTEM ISSUES Chair: John Carter, University of Utah Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions Aamer Jaleel, University of Maryland, College Park Bruce Jacob, University of Maryland, College Park A Unified Compressed Memory Hierarchy Erik Hallnor, University of Michigan Steven Reinhardt, University of Michigan A Performance Comparison of DRAM Memory System Optimizations for SMT Processors Zhichun Zhu, University of Illinois at Chicago Zhao Zhang, Iowa State University Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications Lawrence Spracklen, Sun Microsystems Yuan Chou, Sun Microsystems Santosh G. Abraham, Sun Microsystems 12:30-1:30 Lunch (Provided) 1:30-3:30 SESSION 6: INDUSTRIAL PERSPECTIVES (I) Chair: Sanjay Patel, University of Illinois Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors Hans Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor Zyuban, Rick Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel Tendler, IBM The Soft Error Problem: An Architectural Perspective Shubu Mukherjee, Intel Joel Emer, Intel Steven Reinhardt, University of Michigan Chip Multithreading: Opportunities and Challenges Lawrence Spracklen, Sun Microsystems Santosh G. Abraham, Sun Microsystems Enterprise IT Trends and Implications for Architecture Research Parthasarathy Ranganathan, HP Labs Norman Jouppi, HP Labs 3:30-4:00 Break 4:00-6:00 SESSION 7: INDUSTRIAL PERSPECTIVES (II) Chair: Wen-Mei Hwu, University of Illinois The Cell Processor Peter Hofstee, IBM Panel: New Opportunities for Computer Architecture Research: An Industrial Perspective Organizer: Wen-Mei Hwu, University of Illinois 7:00-10:00 Evening Social Activity: Boat Tour of the San Francisco Bay Wednesday February 16, 2004 ============================== 8:00-9:00 SESSION 8: EVALUATION METHODOLOGIES Chair: Pradip Bose, IBM Characterizing and Comparing Prevailing Simulation Techniques Joshua J. Yi, Freescale Semiconductor Sreekumar V. Kodakara, University of Minnesota Resit Sendag, University of Rhode Island David J. Lilja, University of Minnesota Douglas M. Hawkins, University of Minnesota Transition Phase Classification and Prediction Jeremy Lau, University of California, San Diego Stefan Schoenmackers, University of California, San Diego Brad Calder, University of California, San Diego 9:00-10:00 SESSION 9: SOFTWARE DEBUGGING SUPPORT Chair: Yan Solihin, North Carolina State University SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs Feng Qin, University of Illinois Shan Lu, University of Illinios Yuanyuan Zhou, University of Illinois Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE Marc L. Corliss, University of Pennsylvania E. Christopher Lewis, University of Pennsylvania Amir Roth, University of Pennsylvania 10:00-10:30 Break 10:30-12:30 SESSION 10: MULTIPROCESSORS AND MULTITHREADING Chair: Christos Kozyrakis, Stanford University Unbounded Transactional Memory C. Scott Ananian, MIT Krste Asanovic, MIT Bradley C. Kuszmaul, MIT Charles E. Leiserson, MIT Sean Lie, MIT Improving Multiple-CMP Systems Using Token Coherence Michael R. Marty, University of Wisconsin-Madison Jesse D. Bingham, University of British Columbia Mark D. Hill, University of Wisconsin-Madison Alan J. Hu, University of British Columbia Milo M.K. Martin, University of Pennsylvania David A. Wood, University of Wisconsin-Madison Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture Dhruba Chandra, North Carolina State University Fei Guo, North Carolina State University Seongbeom Kim, North Carolina State University Yan Solihin, North Carolina State University SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors Youtao Zhang, University of Texas at Dallas, Lan Gao, University of California, Riverside, Jun Yang, University of California, Riverside, Xiangyu Zhang, University of Arizona Rajiv Gupta, University of Arizona 12:30 End of Conference ****************************************************************** * * * MoBS: Workshop on Modeling, Benchmarking, and Simulation * * http://www.arctic.umn.edu/MoBS * * * * * ****************************************************************** Held in conjunction with the 32nd Annual International Symposium on Computer Architecture Madison, Wisconsin June 4-5, 2005 Overview: ========= With few exceptions, simulation is the quantitative foundation for virtually all computer architecture research and design projects -- from microarchitectural exploration to hardware and software trade-offs to processor and system design. However, its continued efficacy is limited by problems such as increasing complexity, additional critical constraints (e.g. power consumption, reliability, etc.), an ever expanding design space, benchmark suite quality and coverage, and radical changes in processor architectures to compensate for technological changes (i.e. reduced transistor widths, etc.). The primary goals of this workshop are to accelerate the development of simulation technologies that are necessary to support the research of future generation architectures and to encourage the advancement of under-researched. areas related to computer architecture measurement, such as modeling, benchmark implementation and benchmark suite construction, and formal methods of design space exploration and performance analysis. Topics of interest include, but are not limited to: * New or efficient techniques to model performance, power, reliability, etc. * Accurate but efficient alternatives to cycle-accurate, execution-driven simulation * Simulator verification, flexibility and reusability * Reduced simulation time techniques * Efficient design space exploration * Development of parameterizable, flexible benchmarks * Formal methods for benchmark suite construction or benchmark suite sub-setting * Techniques to measure the characteristics (weak spots, coverage, etc.) of a benchmark suite * Analytical and statistical processor modeling * Choosing processor and memory simulation parameters Submission Guidelines: ====================== The authors should submit a 200 word or less abstract by 9 PM (CST) March 7, 2005 to the workshop website. The full paper should be 5000 words or less and should be submitted in pdf format by 9 PM (CST) March 14, 2005. Papers that are excessively long may be rejected without review. Co-Organizers and Program Co-Chairs: ==================================== Lieven Eeckhout Ghent University leeckhou@elis.ugent.be Joshua J. Yi Freescale Semiconductor jjyi@ece.umn.edu Program Committee: ================== David I. August Princeton University Pradip Bose IBM Research T.J. Watson Brad Calder University of California, San Diego Lizy Kurian John University of Texas at Austin David J. Lilja University of Minnesota at Twin Cities Peter Magnusson Virtutech Jim Smith University of Wisconsin - Madison ------------------------------------------------------------------------- CALL FOR PAPERS ANCHOR 2005 Advanced Networking and Communications Hardware Workshop http://www.ece.northwestern.edu/anchor Held in conjunction with the 32nd Annual International Symposium on Computer Architecture (ISCA 2005) Madison, Wisconsin, June 4-8 2005 Workshop Overview: The rapid expansion of networking applications and data traffic are leading to new specialized network component designs that would keep up with the growing field of networking and communications. Network component design becomes more challenging as the performance and usage of communication networks increase. This workshop focuses on the architectural design approaches for packet-switched networks. From sensor to storage area networks, packet-switched networks are utilized in a wide range of system domains. Furthermore, the workshop aims at providing a forum for scientists and engineers from academia and industry to discuss their latest research on emerging network services. There is a growing interest in extensible networks, overlay networks, and grid computing. Higher layer processing built in hardware can powerfully support these networks and computational styles. This year's workshop will be looking for contributions that will benefit these communities. Workshop Topics: Topics of particular interest include, but are not limited to: - Switch and router architectures (including optical and fiber channel networks) - Communications and network processors - Co-processors (classification, search engine, traffic manager, etc.) - Specialized offload engines (protocol offload engines, I/O adapters, etc.) - Architectures for security applications - Architectures for processor-memory interconnection - Hardware accelerators for emerging network services (overlay, extensible, grid computing, etc.) - Application-specific designs (compression, QoS, etc.) - Power-efficient architectures - High-level software for networking hardware Submission Guidelines: - Submit a 200-word abstract including title and complete author list in email (plain text preferred) to anchor@ece.northwestern.edu by March 25th, 2005. - Submit a 6000-word manuscript in email (pdf or ps format) to anchor@ece.northwestern.edu by April 1st, 2005. Notification of acceptance/rejection will be sent out on May 2nd. Organizers: Taskin Kocak, University of Central Florida, tkocak@cs.ucf.edu Gokhan Memik, Northwestern University, memik@ece.northwestern.edu Program Committee: Brad Calder, UCSD Maria Gabrani, IBM Research ^??? Zurich Jorge Garc???a, UPC Mark Heinrich, UCF Dirk Hoenicke, IBM T.J. Watson Bill Mangione-Smith, UCLA Steve Melvin, O'M&M Christian Sauer, Infineon Raj Yavatkar, Intel ------------------------------------------------------------------------- The 19th ACM International Conference on Supercomputing (ICS05) http://ics05.csail.mit.edu/ =============================================================== June 20 - 22, 2005 (Workshop Tutorials - June 19th) Cambridge, Massachusetts, USA Call for Papers ICS is the premier international forum for the presentation of research results in high-performance computing systems. Topics of interest include, but are not limited to, the following: -- Architecture including power-aware, parallel I/O, grid-based, web-based, continuous monitoring, self-healing, fault-tolerant, embedded. -- Productivity including benchmarks, performance evaluation studies, specialized languages, program development tools. -- Systems including compilers, operating systems, schedulers, runtime optimization -- Applications including numeric and non-numeric, scientific, biological, industrial, massive sensory processing. -- Theoretical underpinnings of any of the above topics as well as analysis and experimental evaluation of systems. The conference also includes invited talks, tutorials, workshops, panels, and exhibits. Important Dates ------------------- Abstract Submission: February 8, 2005 Paper Submission: February 15, 2005 Author notification: April 13, 2005 Final papers: May 16, 2005 More information, including the complete ICS05 Call for Papers, can be found on the conference website http://ics05.csail.mit.edu/ Please forward this call on to other mailing lists. Please use the following website to add (or remove) your name to the announcement list, or to suggest mailing lists to be added (or removed). http://lists.csail.mit.edu/mailman/listinfo/ics05-announce Failing that, send email to ics05-postmaster@csail.mit.edu. Steve Heller Director, SunLabs East, Sun, Sun Microsystems, Inc. Publicity Chair, ICS05 ------------------------------------------------------------------------- * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe